1. Field of the Invention
The present invention relates generally to two phase voltage signal generating circuits and more particularly is directed to a two phase voltage signal generating circuit suitable for being applied to a circuit such as a sample-and-hold circuit of, for example, an analog-to-digital converting circuit which requires two phase pulse signals of phases opposite to each other.
2. Description of the Prior Art
A sample-and-hold circuit 1 of an analog-to-digital converting circuit has hitherto been proposed which includes a diode bridge circuit 2 as shown in FIG. 1. Reference numeral 3 designates its drive circuit which supplies a pulse signal from a pulse generating circuit 4 through a transformer 5 to drive terminals P1 and P2 of the diode bridge circuit 2 to thereby make diodes D1 to D4 of the diode bridge circuit 2 forward-biased and then turned on. Thus, an input voltage VI at an input terminal 6 is sampled in a capacitor 8 connected to an output terminal 7 through signal terminals P3 and P4 of the diode bridge circuit 2. Thereafter, the diode bridge circuit 2 is reverse-biased to be turned off, whereby the sampled voltage is held by the capacitor 8 and then developed at the output terminal 7 as an output voltage V0.
Since the drive circuit 3 employs the transformer 5, it is quite inconvenient for the sample-and-hold circuit 1 to be formed as an integrated circuit (IC). To solve this problem, such a circuit as shown in FIG. 2 is proposed in which two pulse signals .phi..sub.1 and .phi..sub.2 of phases opposite to each other are generated from a two phase pulse signal generating circuit 11 and then supplied across drive terminals P1 and P2 of a diode bridge circuit 12.
In FIG. 2, in the sample-and-hold circuit 1, the two phase pulse signals .phi..sub.1 and .phi..sub.2 of phases opposite to each other derived from the two phase pulse signal generating circuit 11 are supplied through D.C. blocking capacitors 13 and 14 to the drive terminals P1 and P2 of the diode bridge circuit 12. In this case, during the interval in which the pulse signal .phi..sub.1 of positive phase changes from low potential to high potential (accordingly, in which the pulse signal .phi..sub.2 of opposite phase changes from high potential to low potential), all diodes D1 to D4 connected to the bridge sides of the diode bridge circuit 12 are turned on, whereby the input voltage VI applied to the signal input terminal P3 from an input terminal 6 is supplied through the diodes D1 to D4 to a sampling-and-holding capacitor 15 connected to a signal output terminal P4 and then sampled therein. Subsequently, in the interval during which the pulse signal .phi..sub.1 of positive phase changes from high potential to low potential (accordingly, during which the pulse .phi..sub.2 of opposite phase changes from low potential to high potential), the diodes D1 to D4 are all turned off, whereby the sampled voltage in the sampling-and-holding capacitor 15 is held and then delivered to an output terminal 17. This sampled voltage is digitally converted in the circuit at the succeeding stage.
The two phase pulse signal generating circuit 11 includes a differential amplifying circuit consisting of a pair of transistors 21 and 22 whose emitters are connected together to a constant current source 23. An input pulse of, for example, 1/2 duty ratio is supplied from a drive signal source 24 to the base of the transistor 21, while a reference voltage from a reference voltage source 25 is supplied to the base of the other transistor 22. From respective connection points between the collectors of the transistors 21 and 22 and output resistors 26 and 27 the pulse signals .phi..sub.2 and .phi..sub.1 of opposite and normal phases are delivered through buffer amplifying circuits 28 and 29, respectively.
The two pulse signals .phi..sub.1 and .phi..sub.2 are supplied through the D.C. blocking capacitors 13 and 14 to the diode bridge circuit 12, whereby the diode bridge circuit 12 is disconnected in D.C. manner from the two phase pulse signal generating circuit 11 so as not to influence the sampled voltage held in the sampling-and-holding capacitor 15. Further, in order to avoid bad influence of the capacitors 13 and 14, a discharge diode D5 is connected between the drive terminals P1 and P2 of the diode bridge circuit 12. As a result, when the diode bridge circuit 12 is turned off, the charges stored in the capacitors 13 and 14 are discharged through the discharge diode D5.
By the way, in the prior art two phase pulse signal generating circuit 11 of the circuit arrangement shown in FIG. 2, when the timing at which the pulse signal .phi..sub.1 of positive phase and the pulse signal .phi..sub.2 of opposite phase are inverted is displaced or when the wave forms thereof upon inverting are not symmetrical to each other, the absolute value .vertline..phi..sub.1 -.phi..sub.2 .vertline. of the voltages applied to the drive signal terminals P1 and P2 of the diode bridge circuit 12 is partly fluctuated (if the phases of the pulse signals .phi..sub.1 and .phi..sub.2 are perfectly opposite to each other, the absolute value .vertline..phi..sub.1 -.phi..sub.2 .vertline. is constant), and there is then a defect that the above fluctuated component is leaked to the signal output terminal P4. In practice, when the circuit arrangement shown in FIG. 2 is applied as the two phase pulse signal generating circuit 11, due to variable of characteristics of the transistors 21 and 22 which constitute the differential amplifying circuit variable tolerance of the load resistors 26 and 27, stray capacitance of each circuit element portion, variable inductances of leads and the like, it is not possible that the inverting operations of the transistors 21 and 22, namely, the phases and waveforms of the two pulse signals .phi..sub.1 and .phi..sub.2 are made coincident with each other.